Conventional methods for the production of silicon substrates for semiconductor technical devices and associated silicon substrates are described in the following, wherein the silicon substrates are processed with etching procedures.
The U.S. Pat. Nos. 6,198,150 A and 6,180,466 B1 describe silicon substrates for semiconductor technological devices, and wherein the structures of the silicon substrates are furnished with a positive profile having a determined slope angle and are covered with a mask, wherein the structures include an upper part, which includes a mask under etching, where the depth of the mask under etching is approximately equal to the lateral dimension, and the residual part, wherein side walls are present with a defined slope angle. Furthermore the production of shallow trench isolation structures is described in the U.S. Pat. No. 6,180,466 B1, wherein the structures are employed in the semiconductor industry in connection with the production of ULSI semiconductor devices. Here highest integrated circuits are of concern, wherein the packing density of the active regions on the chip is constantly increased up to the limits of the presently produceable structures by advancing minimization of the vertical and of the lateral dimensions of the structures and the further development of electronic semiconductor elements is advanced. The dimensions of the structures are in the sub micrometer region, typically in the nano meter region of up from 180 to 250 nano meters. The wet chemical etching of silicon substrates is described in the document J. P. John et al.: Journal electrochemical society, volume 140, No. 9 (1993), 2622-2625. For example mixtures of nitric acid (HN03), fluoric acid (HF) and water can be employed for this purpose. The etching process runs completely isotropic in this case, that is the mask under etching is nearly as large as the etching depth. Limits for the application of this method result from the advancing minimization of the lateral structural dimensions, which minimization results from the requirement of increasing miniaturerization of the device elements of the microsystem technology.
An aniso-tropic wet chemical structuring of silicon according to H. Seidel, L. Csepregi, A. Heuberger, H. Baumgaertel: Journal electrochemical society, volume 137, No. 11, Nov. 1990, 3612-3632,4, respectively, B. Kim, D. D. Cho: Journal electrochemical society, volume 145, No. 7, Jul. 1998, 2499-2508 is possible by employment of an alkaline etching solution preferring directions, such as potassium hydroxide, lithium hydroxide, or sodium hydroxide. The non iso-tropic character of the etching is based on the different dissolution speeds of the silicon in the various crystal planes. The <111>-plane is most slowly abraded and therefore operates as a structural limitation. During etching of <100>-silicon thus there result frustrated pyramid like recesses where the (111)-faces form the structural walls with a defined angle of 54.74 degrees. With a structural width bM in the etching mask, there can be achieved a maximum etching depth At of
      A    t    =            b      M              √      2      
Since the position of the crystal planes is fixed according to angle and grid, the realization possibilities for microstructures are substantially limited relative to lateral shape and cross-sectional shape of the etched trenches.
Various plasma supported silicon etching processes have been developed in connection with the quick development of semiconductor technology. A multitude of possible plant concepts for plasma etching plants and a multitude of process parameters enable the variation of the etching processes over a wide region. The plasma etching processes are associated in principle and in particular with the advantage, that an anisotropic structuring is possible independent of the crystal orientation.
Plasmachemical silicon etching processes which in most cases are based on fluorine chemistry are described for example in the printed document H. von Boenig: Fundamentals of plasma chemistry and technology, p. 174, The research Institute of plasma chemistry and technology Carlsbad, Calif.
If silicon is for example etched in pure SF6 plasma or (SF6: sulfur hexa fluoride) this process usually runs isotropic, sets that the mask under etching u is approximately equal to the etching depth At.
An anisotropy of the etching process can be obtained in the following way amongst others:
A method under employing of chlorine, bromine, and fluorine chemistry is described in the printed document I. W. Ragelow, H. Loeschner: journal vacuum science and technology, B 13 (6), November/December 1995, 2394-2399 and K.-M. Chang ,T.-H. Yeh, I.-C. Deng, H.-C. Lin: journal of applied physics—Sep. 1, 1996, volume 80, issue 5, 3048-3055, wherein the lateral etching by side wall passivation is prevented. For this purpose the composition of the etching gas is adjusted such that during the etching process also such chemical reactions occur which reactions lead to the covering of the side walls with etch resistant layers.
The high expenditure for the safety technology as well as the gas supply and gas discharge for assuring environmental compatibility is a problem of this method.
A further method under employing of fluorine chemistry in connection with oxygen is described in I. W. Rangelow, H. Loeschner: Journal vacuum science and technology, B 13 (6), Nov. /Dec. 1995, 2394 2399, wherein a mixture of SF6 and oxygen is employed as an etching gas. The silicon reacts with the oxygen species to SiOx in the structures. The oxygen layer is quick to be again removed at the floor by fluorine radicals supported by ion impact as compared with the side walls, such that the etching process obtains a preferred direction. An optimum ratio between sufficient side wall passivation and high etching speed is very difficult to adjust. The control of the passivation limits the achievable etching depth.
Another method employing cryogenic processes in connection with SF6/O2 chemistry is described in the printed document I. W. Ragelow, H. Loeschner: journal vacuum science and technology, B 13 (6), Nov. /Dec. 1995, 2394-2399, wherein a high concentration of reactive etching species is the precondition to obtain high etching speeds. In this case however, a more intense etching attack occurs also on the side walls. The probability of spontaneous reactions between silicon and fluorine at the side walls is reduced drastically by cooling of the substrates to temperatures of about −110 degrees centigrade. The lateral etching rate decreases together with the chemical reaction rate. However, an intensive ion impact occurs at the floor of the structures. This intensive ion impact generates radical places and excites reactive particles such that chemical reactions occur furthermore. A clearly increased vertical etching rate results therefrom.
The methods for etching described in the printed documents U.S. Pat. Nos. 4,902,377, 4,855,017 as well as JP 08-186095 A and JP 04-0282229 A have been developed for the generation of sub micrometer structures with a positive etching profile. The thickness of the structures amounts to at most one micrometer and a rounded off profile with otherwise vertical side walls results.
Technological solutions have been worked out for this application region and also process parameters have been optimized. The methods are suitable for example for the contact hole etching. In fact positive etching profiles of the recited order of magnitude can be generated with this method however this is not the case for larger etching depths.
The described methods cannot be applied for device elements of the microsystem technology, since the structural dimensions in the micro-system technology are by one to two orders of magnitude larger. In this case the etching rates of the recited etch processes are much too low and the influence of the indicated process modifications or process combinations can be neglected with respect to the resulting etching product.
All recited methods are referring to the nano meter region, which nano meter region plays a particular important role in the semiconductor industry. A simple taking over of the described etching processes into the micrometer region for microsystem technological device elements, in particular in the region of about 10 micrometers to about 500 micrometers cannot be achieved. In addition the structural dimensions in the microsystem technology are by two to three orders of magnitude larger as in the semiconductor technology for the production of microelectronic device elements.
Based on the fact that etching processes of the semiconductor technological methods for the structuring of silicon substrates in the nano meter regions cannot be taken over in a simple way to the micrometer region for structuring of microsystem technological device elements, a further developed etching process (advanced silicon etch process—ASE-process) is described in the printed patent document DE 4241045 C 1 for larger, in the micrometer region etchable and suitable silicon substrates with structures in the micrometer region, wherein a cyclical process for the - generation of structures with vertical side walls is performed, which process is composed out of alternating deposition steps and etching steps in the kind of intervals. During the intervals of deposition a passivation of the complete substrates surface occurs by the deposition of a polymer layer. 4241045 C1 for larger, in the micrometer region etchable and suitable silicon substrates with structures in the micrometer region, wherein a cyclical process for the generation of structures with vertical side walls is performed, which process is composed out of alternating deposition steps and etching steps in the kind of intervals. During the intervals of deposition a passivation of the complete substrates surface occurs by the deposition of a polymer layer.
A problem comprises that during the etch interval, the polymer layer is removed on all horizontal planes by ion impact. The silicon laid bare reacts with fluorine to volatile reaction products at the floor of the structures. The covering with a polymer at the vertical side walls remains intact. The horizontal layer disposed in the depth and furnished with the polymer is freed from the polymer by ion impact, such that the next etching step produces an advancing etching depth At.
A problem comprises that the wall roughness of the etched structures is fairly high. Etching depths At in the order of magnitude of microsystem technological device elements, however the side walls of the etching profile as pregiven, remain formed vertically.
Essential features of the ASE process include:                realization of etching depth of from 10 to 500 micrometer        achievable aspect ratio: larger than 25        slope angle in the side walls: 90 degrees or very nearly 90 degrees        mask under etching is not present or approaches zero        arbitrary lateral shape of the structures (for example channel structures, passage holes through the silicon wafer, comb like structures, grid structures) can be realized        application of conventional etching masks (for example SiO2, photo resist)        etching rate: three to five micrometers per minute        
In order to decrease the wall roughness of the generated side walls there is described as a further development a method for the plasma etching for generation of etching profiles in silicon substrates in the printed document of B. Volland et al., Journal of Vacuum Science and Technology B, Microelectronics proceedings and phenomena volume 17 No. 6 Nov. and 1999, pp. 2768 - 2771, wherein the silicon substrate is covered with a mask and the following steps are performed:
the isotropic etching according to the method of the printed document DE 4241045 C 1 is substituted by an anisotropic etching step,
an anisotropic etching with alternatingly following successively polymerisation steps in a C4F8 plasma and etching steps in the SF6 plasma such that the etching depth At with constant mask under etching u is enlarged and the side walls of the structure are covered with a polymer, as well as repetitions of the preceding steps until the predetermined etching profile is generated.
The removal of the polymer from the floor of the etching front and in part from the side walls of the etch structure is performed with each of the SF6 plasma steps. The problem comprises that undesired deviations of the etching profile as is shown in FIG. 2 occur during etching of structures with high aspect ratios, which corresponds to the quotient between etching depth and structural breadth.
Here also regions with slightly negative and slightly positive etching profiles can be generated, which etching profiles deviate from the predetermined etching profiles with the desired vertical side walls. Amongst others the following causes exist for this:
the regions with positive etching profile are generated here at large etching depth in narrow trenches through                shading effects for the arriving ions,        problems at the discharge transport of the etching species and the discharge transport of reaction products        ion straying and ion braking and deceleration.        
The regions with a negative etching profile are generated by:                deflection of ions in the direction of the side walls in the middle region, whereby an increased attack of the passivation layer is present at the side walls, and        the deflection of ions in the direction of the side walls based on the changed electrical field at the mask edges present below the etching mask.        
The recited problems depend on the layouts and on the etching depth and are by no means desired. In addition, the positive regions and the negative regions of the etching profiles cannot be adjusted independently from each other.
On the contrary, in order to be able to oppose angle deviations from the desired vertical side walls and in order to control the generation of vertical side walls, the method has been optimized.
Based on the present state of the art it has to be determined that presently hardly any technological possibilities exist for varying the etching profile in the silicon structuring. These possibilities are limited essentially to the following two variations:    a) completely iso-tropic etching (for example by way of SF6-plasma) as illustrated in FIG. 1 as a conventional structure.    b) Etching for realization of silicon structures with completely vertical side walls having mask under etchings close to zero as are shown in FIG. 2 according to the printed document DE 4241045 C1 and the printed document of B. Volland et al., Journal of Vacuum Science and Technology B, Microelectronics proceedings and phenomena volume 17 No. 6, November 1999, pp. 2768-2771.
A decisive problem of all silicon substrates with etching profiles with vertical side bowls and negative etching profiles with divergence side walls within the silicon substrate comprise that the release of mold cast parts disposed in the etching profile is difficult or, respectively, not possible.